1. Field of the Invention
The present invention relates to a semiconductor device such as a semiconductor device of a system-in-package type.
2. Description of Related Art
Multiple functions and high performance in a semiconductor device are requested in accompaniment with a progress of an information processing technique. As a technique to fulfill such a request, a semiconductor device of a system-in-package (“SiP”) type is known, in which a plurality of LSIs are sealed in a single package. In the semiconductor device of the system-in-package type, miniaturization of package size and reduction of the number of pins are requested. In view of these, the system-in-package type semiconductor device have prevailed, in which a logic chip and a memory chip are mounted without including any external terminal for outputting data directly from the memory chip (hereinafter to be referred to as an external memory terminal).
In a package having no external memory terminal, it may be difficult to perform a memory test after a system is assembled in the package. In the package having no external memory terminal, a technique has been known for performing a test on a memory chip through an external terminal for inputting/outputting data to/from the logic chip in the package and a logic chip test circuit, as shown in Japanese Patent Application Publication (JP-P2004-158098A).
FIG. 1 is a circuit diagram showing a configuration of a conventional system-in-package type semiconductor device 101. The semiconductor device 101 includes a logic chip 102 and a memory chip 103. The semiconductor device 101 further includes a bus control terminal 105, a data input/output terminal 106, a clock supply terminal 107 and an address/control signal supply terminal 108. The terminals are connectable to a tester 104. The semiconductor device 101 has no terminal dedicated to the memory chip 103 as an external terminal. Thus, when the test is performed on the memory chip 103, the logic chip 102 is set to a test mode so that a data and signals are transferred through a test circuit to the memory chip 103 and an access is made through a logic terminal to the memory chip 103.
A bus release control signal I/O_en is supplied through the bus control terminal 105 to control bus release of a test circuit in a memory chip data write. A register setting data DATA is supplied through the data input/output terminal 106. In addition, a result of a memory chip data read is outputted through the data input/output terminal 106. A clock signal CLK is supplied through the clock supply terminal 107, to control the memory chip 103. An address signal Add and a control signal Ctrl are supplied through the address/control signal supply terminal 108. The address signal Add specifies an address of the memory chip 103 whereas the control signal Ctrl is used for controlling the memory chip 103.
As shown in FIG. 1, the logic chip test circuit is provided with a first flip-flop 111 to a fourth flip-flop 114, to allow a high-speed operation. The flip-flops 111 to 114 are formed on signal lines for a high frequency, to reduce a variation in signal propagation.
A data signal supplied to the data input/output terminal 106 is transferred to the memory chip 103 through the flip-flops. Therefore, the data signal is supplied to the memory chip 103 with a delay of several clock pulses. FIG. 2 is a timing chart showing an operation of the system-in-package type semiconductor device 101 provided with 2-stage flip-flops, in which the first flip-flop 111 and the second flip-flop 112 are disposed in series whereas the third flip-flop 113 and the fourth flip-flop 114 are disposed in series. Referring to FIG. 2, the data signal supplied through the data input/output terminal 106 is supplied to the memory chip 103 with a delay of 2 clock pulses in case of the data write into the memory chip 103. In contrast, in case of the data read from the memory chip 103, the data signal is outputted from the memory chip 103 through the data input/output terminal 106 with a delay of 2 clock pulses. That is, when the data signal is write into and read from the memory chip 103, a delay of 4 clock pulses is caused in total.
FIG. 3 is a timing chart showing an operation of the system-in-package type semiconductor device 101 when the data read and the data write are continuously performed to the memory chip 103. Usually, a continuous operation to the memory chip 103 cannot be performed unless the data write is performed immediately after the data read. Thus, in case of the operation shown in FIG. 3, it is assumed that a read command RED is supplied in 4 clock pulses after a first write command WRT, and then a write command WRT is supplied again in 5 clock pulses after the read command. In this case, the data input/output terminal 106 are simultaneously used for data input and data output at the supply of a second write command. That is to say, the simultaneous operation of the data read and the data write cannot be operated. Thus, in the conventional circuit configuration using the flip-flops, it is impossible to perform the operation test in which the data read and the data write are continuously performed.
In other words, in the conventional system-in-package type semiconductor device 101, when the memory chip 103 is tested in a high-speed operation through the logic chip test circuit, a test data signal is synchronized with the clock signal in the logic chip 102. Therefore, a clock delay is caused due to the flip-flops when the data signal is supplied to the memory chip 103 or outputted from the memory chip 103. Therefore, it is difficult to test a continuous operation of the data read and the data write subsequent to the data read to the memory chip due to the clock delay.